About Event

System Verilog is the industry IEEE-1800 standard combining the hardware description language and hardware verification language. This course focuses on the use of advanced verification features in System Verilog. Students will learn the step-by-step processes of creating flexible verification components, which form the basis of modern industry-standard methodologies
PREREQUISITE
Knowledge in System Verilog and knowledge of
VHDL, Verilog, C/C++, and some hardware verification experience.
KEY CONTENTS OF THE SEMINAR
1. Introduction to Design and Verification of an IC
2. Introduction to System Verilog language
3. Interfaces, Clocking blocks, Modports
4. Constraint based Randomization
5. Coverage Metrics in verification
6. Assertions based verification
Note: 3,4,5,6 - Will be pure hands-on Experience